D0

PU0

PT0

MU0

MT0

HU0

HT0

C7

C11

MAG0

0

D1

PU1

PT1

MU1

MT1

HU1

HT1

C8

C12

MAG1

0

D2

PU2

PT2

MU2

MT2

HU2

C5

C9

C13

MAG2

0

D3

PU3

PT3

MU3

C4

HU3

C6

C10

C14

0

0

D4

HAM

HAM

HAM

HAM

HAM

HAM

HAM

HAM

FOUND

0

D5

000000000

PBLF

D6

0000000000

D7

0000000000

COLUMN

0123456789

Page number : - MAG = magazine, PU = page units, PT = page tens.

Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens.

PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits.

Table 1 : Row 25 received page control data format

8/30 READING

8/30 packet is read at row 23 equivalent address.

R8 register must be programmed with D3, D2,

D0 = 0 and D2 = 1 (8/30 selection).

R9 register must be programmed with 23 (17h).

R10 register value corresponds to the position of

the byte to be read (from 0 to 39).

R11A contents the value of the needed byte.

D7

D6

D5

D4

D3

D2

D1

D0

*

*

*

*

*

EVEN

OFF

TC

SEL11B

R0

Mode 0

TA

7 + P/

8 BIT

ACQ.

ON/OFF

8/30

ENABLE

DEW/

FULL

FIELD

TCS

ON

T1

T0

R1

Mode 1

*

*

ACQ

CCT

A1

ACQ.

CCT

A0

TB

START

COLUMN

SC2

START

COLUMN

SC1

START

COLUMN

SC0

R2

Page request adress

*

*

*

PRD4

PRD3

PRD2

PRD1

PRD0

R3

Page request data

*

*

*

*

**A1

A0

R4

Display chapter

BKGND

OUT

BKGND

IN

COR

OUT

COR

IN

TEXT

OUT

TEXT

IN

PON

OUT

PON

IN

R5

Display control (normal)

BKGND

OUT

BKGND

IN

COR

OUT

COR

IN

TEXT

OUT

TEXT

IN

PON

OUT

PON

IN

R6

Display control

(newsflash / subtitle)

STATUS

ROW

BTM/TOP

CURSOR

ON

CONCEAL/

REVEAL

TOP/

BOTTOM

SINGLE/

DOUBLE

HEIGHT

BOX ON

24

BOX ON

1-23

BOX ON

0

R7

Display mode

*

*

*

*

CLEAR

MEM.

8/30

SELECT

A1

A0

R8

Active chapter

*

*

*

R4

R3R2R1

R0

R9

Active row

*

*

C5

C4

C3

C2

C1

C0

R10

Active column

D7

(R/W)

D6

(R/W)

D5

(R/W)

D4

(R/W)

D3

(R/W)

D2

(R/W)

D1

(R/W)

D0

(R/W)

R11A

Active data

60Hz

0

0

0

0

0

0

VCS

signal

quality

R11B

Status

* Reserved register bits : must be set to 0

↵

↵

↵

↵

↵

↵

↵

↵

Table 2 : Register specification

REGISTER MAP (see Table 2)

Registers R0 to R10 are write only whilst R11A is a

read/write and R11B is a read only register respect

to the microprocessor.

The automatic succession on a byte basis is indi-

cated by the arrows in Table 2.

In the normal operating mode TA, TB and TC

should be set to logic level 0.

After power-up the contents of the registers are as

follows : all bits in registers R0 to R11A are cleared

to zero with the exception of bits D0 and D1 in

registers R5 and R6 which are set to logical one.

After power-up all the memory bytes are preset to

hexadecimalvalue 20 H (space) with the exception

of the byte corresponding to row 0 of column 7 of

chapter 0 which is set to the value corresponding

to ”alpha white” hexadecimal value 07 H.

STV5342

13/20