SC202F

14

Applications Information (continued)

(connected to the SNS pin) away from the LX node

as shown in Figure 2 to minimize noise and magnetic

interference.

Minimize the resistance from the OUT and GND pins

to the load. This will reduce errors in DC regulation

due to voltage drops in the traces.

The two smaller exposed pads on this package should

not be connected to any traces. The area beneath

these two pads must be kept clear so that they do

not make electrical contact with any traces, including

ground.

5.

6.

3.5m m

CT L0

CT L1

CT L3

LX

(no

connection

needed)

SN S

GND

IN

OUT

3.8m m

S C 202F

be electrically

connected to the P C B .

Figure 2 — Recommended PCB Layout