ESP32-D0WD datasheet(21/60 Pages) ESPRESSIF

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3. Functional Description

3.1.3 External Flash and SRAM

ESP32 supports multiple external QSPI flash and SRAM chips. More details can be found in Chapter SPI in

the ESP32 Technical Reference Manual. ESP32 also supports hardware encryption/decryption based on AES to

protect developers’ programs and data in flash.

ESP32 can access the external QSPI flash and SRAM through high-speed caches.

• Up to 16 MB of external flash can be mapped into CPU instruction memory space and read-only memory

space simultaneously.

– When external flash is mapped into CPU instruction memory space, up to 11 MB + 248 KB can be

mapped at a time. Note that if more than 3 MB + 248 KB are mapped, cache performance will be

reduced due to speculative reads by the CPU.

– When external flash is mapped into read-only data memory space, up to 4 MB can be mapped at a

time. 8-bit, 16-bit and 32-bit reads are supported.

• External SRAM can be mapped into CPU data memory space. SRAM up to 8 MB is supported and up to 4

MB can be mapped at a time. 8-bit, 16-bit and 32-bit reads and writes are supported.

Note:

After ESP32 is initialized, firmware can customize the mapping of external SRAM or flash into the CPU address space.

3.1.4 Memory Map

The structure of address mapping is shown in Figure 7. The memory and peripheral mapping of ESP32 is shown

in Table 5.

Figure 7: Address Mapping Structure

Espressif Systems

ESP32 Datasheet V3.0

ESP32-D0WD 数据表(PDF) 21 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.