GPUSB101A

© Generalplus Technology Inc.

Proprietary & Confidential

9

Sep 24, 2014

Version: 1.4

6.4. Parallel Bus

There is a parallel bus slave side on GPUSB101A. The host IC as a parallel bus master role. Host IC can use GPIO toggle to implement

signals like section 6.4.3. According to host IC GPIOs number. The customer can select 8 bit mode (5 control pin and 8 data pin) or 4 bit

mode (5 control pin and 4 data pin). Besides Para_int is input pin, others control pin are output pin. If the GPUSB101A has request to

host IC. GPUSB101A may issues Parallel_int pin then host IC must polling the status register and knows what request from GPUSB101A.

6.4.1 The description of parallel bus I/O

Pad name

Type

IO

Description

Para_cdb

I

IOA[0]

Parallel bus for command or data transfer (high is command and low is data)

Para_csb

I

IOA[1]

Parallel bus chip enable (active low)

Para_rdb

I

IOA[2]

Parallel bus write enable (active low)

Para_wrb

I

IOA[3]

Parallel bus read enable (active low)

Para_int

O

IOA[4]

Parallel bus interrupt out

Para_data[7:0]

I/O

IOB[7:0]

Parallel bus bi-directional data

6.4.2 The function of parallel bus

Para_cdb

Para_wrb

Para_rdb

Description

1

0

1

Write command register

1

1

0

Read status register

0

0

1

Write data

0

1

0

Read data

Note1: command register is read only bridge IC.

Note2: status register is read only for host IC.

6.4.3 Timing diagram

8 bit mode

Write command

para_csb

para_cdb

para_wrb

para_data[7:0]

command

T1

T2

T3

T4

T6

Read status

para_csb

para_cdb

para_rdb

para_data[7:0]

status

T1

T2

T7

T8

T6

Write data

para_csb

para_cdb

para_wrb

para_data[7:0]

1st data

2nd data

last data

T1

T2

T3

T4

T6

T5

Read data

para_csb

para_cdb

para_rdb

para_data[7:0]

T1

T2

T7

T8

T6

T5

2nd data

last data

1st data