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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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GD5F1GQ4RE9JS 数据表(PDF) 21 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD5F1GQ4RE9JS 数据表(HTML) 21 Page - GigaDevice Semiconductor (Beijing) Inc. |
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21 / 60 page  SPI(x1/x2/x4) NAND Flash 1G 21 8.7 Read From Cache Quad IO (EBH) The Read from Cache Quad IO command is similar to the Read from Cache x4 command but with the capability to input the 4 dummy bits, followed a 12-bit column address for the starting byte address and a dummy byte by SIO0, SIO1, SIO3, SIO4, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle from SIO0, SIO1, SIO2, SIO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out until the boundary wrap bit. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache quad IO command. Figure8-6. Read From Cache Quad IO Sequence Diagram Command 0 1 2 3 4 5 6 7 EBH CS# SCLK SI(SIO0) SO(SIO1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 A7-0 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 WP#(SIO2) HOLD#(SIO3) 4 5 6 7 Dummy Byte1 Byte2 dummy<3:0>, A11-A8 |
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