GD25B127DPFS datasheet(29/65 Pages) GIGADEVICE

29 / 65 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B127D

7.18.

64KB Block Erase (BE) (D8H)

The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command

must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is

entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block

is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.

The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte address

on SI  CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the

last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is

driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,

the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1

during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is

protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits is not executed.

Figure20. 64KB Block Erase Sequence Diagram

7.19.

Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously

have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low,

followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence.

The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The

command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been

latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase

cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check

the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and

is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

The Chip Erase (CE) command is executed only if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the

Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more sectors

are protected.

Figure21. Chip Erase Sequence Diagram

Command

60H or C7H

CS#

SCLK

Command

D8H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

GD25B127DPFS 数据表(PDF) 29 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25B127DPFS 数据表(HTML) 29 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

数据表下载