GD25LE16CSIG datasheet(34/67 Pages) GIGADEVICE

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1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LE16C

7.29 Erase Security Registers (44H)

The GD25LE16C provides three 512-byte Security Registers which can be erased and programmed individually. These

registers may be used by the system manufacturers to store security and other important information separately from the

main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must

previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command  The

Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command  3-byte

address on SI  CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of

the last address byte has been latched in; otherwise the Erase Security Registers command is not executed. As soon as

CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security

Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The

Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some

unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit

(LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security

Registers will be permanently locked; the Erase Security Registers command will be ignored.

Address

A23-16

A15-12

A11-9

A8-0

Security Register #1

00H

0 0 0 1

0 0 0

Don’t care

Security Register #2

00H

0 0 1 0

0 0 0

Don’t care

Security Register #3

00H

0 0 1 1

0 0 0

Don’t care

Figure31. Erase Security Registers command Sequence Diagram

7.30 Program Security Registers (42H)

The Program Security Registers command is similar to the Page Program command. Each security register contains four

pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL)

bit before sending the Program Security Registers command. The Program Security Registers command is entered by

driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as

CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program

Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)

bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.

At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security

Registers command will be ignored.

Address

A23-16

A15-12

A11-9

A8-0

Security Register #1

00H

0 0 0 1

0 0 0

Byte Address

Security Register #2

00H

0 0 1 0

0 0 0

Byte Address

Security Register #3

00H

0 0 1 1

0 0 0

Byte Address

Command

44H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

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