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GD25LE10CSJG 数据表(PDF) 43 Page - GigaDevice Semiconductor (Beijing) Inc.

部件名 GD25LE10CSJG
功能描述  1.8V Uniform Sector Dual and Quad Serial Flash
PDF  75 Pages
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制造商  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
网页  http://www.gigadevice.com/
标志 GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25LE10CSJG 数据表(HTML) 43 Page - GigaDevice Semiconductor (Beijing) Inc.

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1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LE40C/20C/10C/05C
43
Figure33. Read Security Registers command Sequence Diagram
7.32 Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default
power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status
(WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Deep Power Down Mode, Continuous Read Mode
bit setting (M7-M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI mode. The “Reset (99H)” command
sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low  Sending
Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will take approximately
tRST/tRST_E to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or
suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is
recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.
Figure34. Enable Reset and Reset command Sequence Diagram
Command
0
1
2
3
4
5
6
7
66H
CS#
SCLK
SI
SO
High-Z
Command
0
1
2
3
4
5
6
7
99H
Command
0
1
2
3
4
5
6
7
48H
CS#
SCLK
SI
SO
High-Z
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
MSB
34 35 36 37
33
6
5
4
3
2
1
0
38 39
Data Out1
32
42 43 44 45
41
46 47
40
7
6
5
4
3
2
1
0
7
6
5
7
Data Out2
CS#
SCLK
SI
SO
MSB
Dummy Byte



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