GD25LE05CSEG datasheet(23/75 Pages) GIGADEVICE

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1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LE40C/20C/10C/05C

Figure4. Write Enable for Volatile Status Register Sequence Diagram

7.4 Read Status Register (RDSR) (05H or 35H)

The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any

time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it

is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible

to read the Status Register continuously.

For command code “05H”, the SO will output Status Register bits S7~S0. The

command code “35H”, the SO will output Status Register bits S15~S8.

Figure5. Read Status Register Sequence Diagram

Command

05H or 35H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

S7~S0 or S15~S8 out

MSB

7.5 Write Status Register (WRSR) (01H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be

accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)

command has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS# must be

driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR)

command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be

cleared to 0. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated.

While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In

Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it

is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2,

BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 1-4. The Write Status

CS#

SCLK

Command(50H)

High-Z

GD25LE05CSEG 数据表(PDF) 23 Page - GigaDevice Semiconductor (Beijing) Inc.

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