U74HC4046A

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

18 of 19

www.unisonic.com.tw

QW-R502-461.D



PLL DESIGN EXAMPLE

Fig.15 Frequency Synthesizer.

The parameters of the frequency synthesizer in Fig.15:

Output frequency: 2 MHz to 3 MHz

Frequency steps: 100kHz

Settling time: 1ms

Overshoot: < 20%

The Open-Loop Gain is:

n

o

f

p

K

K

K

K

s

G

s

H











)

(

)

(

20

100kHz

2MHz

f

f

N

step

out

Min







0

3

100kHz

3MHz

f

f

N

step

out

Max







The VCO is set by the values of R1, R2 and C1, R2 = 10 kΩ (adjustable). The values can be determined using the

information in the section “DESIGN CONSIDERATIONS”.

R1 = 10 kΩ; R2 = 10 kΩ; C1 = 500 pF

The VCO gain is:

/ V

s

/

r

10

2

2

3.2

1MHz

0.9)

(V

0.9

2

2f

K

6

CC

L

V























The gain of the phase comparator is:

CC

p

V

K

0.4V / r

4





The transfer gain of the filter is given by:

S

)

(

1

S

1

K

2

1

2

f















Where:

R3C2



and

R4C2



The characteristics equation is:

1 + H(S) × G(S) = 0

This results in:

0

)

(

K

K

K

S

)

(

1

S

2

1

n

v

p

2

1

2

2

































n

v

p

K

K

K

)

(

2

1















n

v

p

n

K

K

K

Damping Value ζ is Defined as follows:

)

(

1

2

1

2

1

2

























n

v

p

n

K

K

K