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TC9208M
Preliminary Data Sheet
which these modes include auto-negotiation
disable procedure for 10/100 speed modes. The
phy configuration information is stored in
EEPROM setting.
The chip requires 27 MHz system clock, dual 2V
and 3.3V power supply and is packaged in PBGA
292.
Block Diagram
From RX MAC
8 GMII/MII
RX/TX MAC's
Address
LoockUp
&
Resolution
Unit
Memory
Interface
&
Arbiter
Queue
Management
EEprom Interface
Configuration
Register
External PHY's
TC9208M
Block Diagram
MDIO
interface
To TX MAC
Rx FIFO
Tx FIFO
Internal
SSRAM
Buffer
Confidential.
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August 1, 2003
Copyright © 2003, IC Plus Corp.
TC9208M-DS-R06