GD25S512MDBIS datasheet(44/87 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S512MD

7.19.

Sector Erase (SE 20H or 4SE 21H)

The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must

previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by

driving CS# low, followed by the command code, and 3-address Byte on SI. Any address inside the sector is a valid address

for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.

The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-Byte address on SI 

CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the

Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose

duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value

of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0

when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A

Sector Erase (SE) command applied to a sector which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bit

is not executed.

Figure 38 Sector Erase Sequence Diagram (ADS=0)

Figure 39 Sector Erase Sequence Diagram (ADS=1)

Figure 40 Sector Erase with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)

Command

20H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

Command

21H

CS#

SCLK

37 38 39

MSB

32 Bits Address

31 30

Command

20H

CS#

SCLK

37 38 39

MSB

32 Bits Address

31 30

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