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STV5345 数据表(PDF) 15 Page - STMicroelectronics |
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STV5345 数据表(HTML) 15 Page - STMicroelectronics |
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15 / 25 page  D7 D6 D5 D4 D3 D2 D1 D0 * * * * * EVEN OFF TC SEL11B R0 Mode 0 TA 7 + P/ 8 BIT ACQ. ON/OFF GHOST ROW ENABLE DEW/ FULL FIELD TCS ON T1 T0 R1 Mode 1 BLOCK SELECT A3 BANK SELECT A2 ACQ. CCT A1 ACQ. CCT A0 TB START COLUMN SC2 START COLUMN SC1 START COLUMN SC0 R2 Page request adress * * * PRD4 PRD3 PRD2 PRD1 PRD0 R3 Page request data * * * * A3 A2 A1 A0 R4 Display chapter BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN R5 Display control (normal) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN R6 Display control (newsflash / subtitle) STATUS ROW BTM/TOP CURSOR ON CONCEAL/ REVEAL TOP/ BOTTOM SINGLE/ DOUBLE HEIGHT BOX ON 24 BOX ON 1-23 BOX ON 0 R7 Display mode * * * A3 CLEAR MEM. A2 A1 A0 R8 Active chapter * * * R4 R3R2R1 R0 R9 Active row * * C5 C4 C3 C2 C1 C0 R10 Active column D7 (R/W) D6 (R/W) D5 (R/W) D4 (R/W) D3 (R/W) D2 (R/W) D1 (R/W) D0 (R/W) R11A Active data 60Hz 0 0 0 0 0 0 VCS signal quality R11B Status * * EROD A1 A0 * * * R12 Page request address * Reserved register bits : must be set to 0 ↵ ↵ ↵ ↵ ↵ ↵ ↵ ↵ Table 2 : Register specification REGISTER MAP (see Table 2) Registers R0 to R10 and R12 are write only whilst R11A is a read/write and R11B is a read only register respect to the microprocessor. The automatic succession on a byte basis is indi- cated by the arrows in Table 2. In the normal operating mode TA, TB and TC should be set to logic level 0. After power-up the contents of the registers are as follows : all bits in registers R0 to R12 are cleared to zero with the exception of bits D0 and D1 in registers R5 and R6 which are set to logical one. After power-up all the memory bytes are preset to hexadecimalvalue 20 H (space) with the exception of the byte corresponding to row 0 of column 7 of chapter 0 which is set to the value corresponding to ”alpha white” hexadecimal value 07 H. REFRESH ON DISPLAY FUNCTION This function allows independently to fill the mem- ory using 3 acquisition circuits when the 4th one refreshes the displayed page. When EROD (D5 of Reg. 12) is 0, refresh on display function is not active. Four teletext pages are filled into memory corresponding to addresses of acqui- sition registers. Two blocks of 8 pages are selected with A3 (D7of Reg. 2) Upper or lower bank of 4 pages is selected with A2 (D6 of Reg. 2). Acquisition circuits are selected with A1/A0 (D5/D4 of Reg. 2). This 2 bits also determine the 1KByte of RAM (the chapter) allocated to each acquisition circuit. When EROD = 1, refresh on display function is active. 3 acquisition circuits store pages as described above. The 4th one stores data into the current displayed chapter. The chapter is selected with addresses A3/A2/A1/A0 (D3/D2/D1/D0 of Reg. 4). Notice that A1/A0 (D1/D0 of Reg. 4) give the circuit number to be used to refresh this displayed chap- ter. That means A1/A0 of refresh on display function (D4/D3 of Reg. 12) have to be written identical to A1/A0 (D1/D0 of Reg. 4), as A2 of acquisition circuit (D6 of Reg. 2) has to be identical to A2 of displayed chapter (D2 of Reg. 4). STV5345 - STV5345/H - STV5345/T 15/25 |
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