8086-2 datasheet(2/30 Pages) INTEL

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8086

Table 1. Pin Description

The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ‘‘Local

Bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to

additional bus buffers).

Symbol

Pin No.

Type

Name and Function

AD15–AD0

2 – 16, 39

I/O

ADDRESS DATA BUS:

These lines constitute the time multiplexed

memory/IO address (T1), and data (T2, T3, TW, T4) bus. A0 is

analogous to BHE for the lower byte of the data bus, pins D7–D0. It is

LOW during T1 when a byte is to be transferred on the lower portion

of the bus in memory or I/O operations. Eight-bit oriented devices tied

to the lower half would normally use A0 to condition chip select

functions. (See BHE.) These lines are active HIGH and float to 3-state

OFF during interrupt acknowledge and local bus ‘‘hold acknowledge’’.

A19/S6,

35 – 38

ADDRESS/STATUS:

During T1 these are the four most significant

address lines for memory operations. During I/O operations these

A18/S5,

lines are LOW. During memory and I/O operations, status information

A17/S4,

is available on these lines during T2, T3, TW, T4. The status of the

A16/S3

interrupt enable FLAG bit (S5) is updated at the beginning of each

CLK cycle. A17/S4 and A16/S3 are encoded as shown.

This information indicates which relocation register is presently being

used for data accessing.

These lines float to 3-state OFF during local bus ‘‘hold acknowledge.’’

A17/S4

A16/S3

Characteristics

0 (LOW)

Alternate Data

Stack

1 (HIGH)

Code or None

Data

S6 is 0

(LOW)

BHE/S7

BUS HIGH ENABLE/STATUS:

During T1 the bus high enable signal

(BHE) should be used to enable data onto the most significant half of

the data bus, pins D15–D8. Eight-bit oriented devices tied to the upper

half of the bus would normally use BHE to condition chip select

functions. BHE is LOW during T1 for read, write, and interrupt

acknowledge cycles when a byte is to be transferred on the high

portion of the bus. The S7 status information is available during T2,

T3, and T4. The signal is active LOW, and floats to 3-state OFF in

‘‘hold’’. It is LOW during T1 for the first interrupt acknowledge cycle.

BHE

Characteristics

Whole word

Upper byte from/to odd address

Lower byte from/to even address

None

READ:

Read strobe indicates that the processor is performing a

memory or I/O read cycle, depending on the state of the S2 pin. This

signal is used to read devices which reside on the 8086 local bus. RD

is active LOW during T2, T3 and TW of any read cycle, and is

guaranteed to remain HIGH in T2 until the 8086 local bus has floated.

This signal floats to 3-state OFF in ‘‘hold acknowledge’’.

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