T25S16AFEPR datasheet(32/74 Pages) HMSEMI

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6.4. Page Program

To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a

Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program

cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to

be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the

same page of memory.

6.5. Sector Erase, Block Erase and Chip Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the

bytes of memory need to be erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector

Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout the entire

memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration tSE tBE or tCE).

The Erase instruction must be preceded by a Write Enable (WREN) instruction.

6.6. Polling during a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or

CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In Progress (WIP)

bit is provided in the Status Register so that the application program can monitor its value, polling it to

establish when the previous Write cycle, Program cycle or Erase cycle is complete.

6.7. Active Power, Stand-by Power and Deep Power-Down Modes

When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select

(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have

completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The

device consumption drops to ICC1.

The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode

(DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode

until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI)

instruction) is executed.

All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as

an extra software protection mechanism, when the device is not in active use, to protect the device from

inadvertent Program or Erase instructions.

HM25Q128A

T25S16AFEPR 数据表(PDF) 32 Page - Shenzhen Huazhimei Semiconductor Co., Ltd