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G682H09SQL1U 数据表(PDF) 12 Page - Global Mixed-mode Technology Inc

部件名 G682H09SQL1U
功能描述  Low Voltage Reset IC
PDF  18 Pages
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制造商  GMT [Global Mixed-mode Technology Inc]
网页  http://www.gmt.com.tw
标志 GMT - Global Mixed-mode Technology Inc

G682H09SQL1U 数据表(HTML) 12 Page - Global Mixed-mode Technology Inc

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Ver: 0.8
Feb 27, 2013
TEL: 886-3-5788833
http://www.gmt.com.tw
12
G682/G683
Global Mixed-mode Technology
Detailed Description
A microprocessor’s (μP’s) reset input starts the μP in a
known state. The G682L/G682H/G683L assert reset to
prevent
code-execution
errors
during
power-up,
power-down, or brownout conditions. Since the sense
pin is separated from power supply, it allows the IC to
monitor added power supply.
They assert a reset signal
whenever the Vsen supply voltage declines below a
preset threshold (VTH-), keeping it asserted for time de-
lay set by capacitor connected to CD pin, after Vsen has
risen above the high reset threshold VTH+ (VTH-+VHYS).
The G683L uses an open-drain output, and the
G682L/G682H have a push-pull output stage. Connect
a pull-up resistor on the G683L’s RESET output to
any supply between 0 and 5.5V. The time delay is set
by external capacitor CD, and internal pull up current ICD.
When the voltage at CD pin exceeds the buffer thresh-
old, typically 0.788V, the RESET output high (RESET
output low). The voltage detector and buffer have
built-in hysterisis to prevent erratic reset operation. The
formula of time delay is T (ms) ≅ 2.7
×CD (nF). Figure1
and Figure2 show Timing and Functional Block Dia-
grams.
Timing Diagram
Figure 1
V
SEN
VTH+
VTH-
V
CC
V
CC
V
CC
0V
0V
tRP
V
SEN
Reset Output
(Active Low), Pin 1
Reset Output
(Active High), Pin 1
CD Threshold, 0.788V
* tRP (ms) ≅ 2.7 × CD (nF) (TYP)
*
0V
V
SEN
VTH+
VTH-
V
CC
V
CC
V
CC
0V
0V
tRP
V
SEN
Reset Output
(Active Low), Pin 1
Reset Output
(Active High), Pin 1
CD Threshold, 0.788V
* tRP (ms) ≅ 2.7 × CD (nF) (TYP)
*
0V



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