Data Sheet

ADF5902

Rev. 0 | Page 21 of 39

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4

DB3

DB2

DB1

DB0

0

0

RON

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

N0

F24

F23

F22

F21

F20

F19

F18

F17

F16

F15

F14

F13

C4(0) C3(1) C2(0) C1(1)

CONTROL

BITS

RESERVED

FRAC MSB WORD

INTEGER WORD

C5(0)

N11

N10

...

N4

N3

N2

N1

N0

0

0

...

00

00

0

NOT ALLOWED

0

0

...

00

00

1

NOT ALLOWED

0

0

...

00

01

0

NOT ALLOWED

.

.

...

.

.

.

.

.

...

0

0

...

01

01

0

NOT ALLOWED

0

0

...

01

01

1

75

0

0

...

01

10

0

76

.

.

...

.

.

.

.

.

...

1

1

...

11

10

1

4093

1

1

...

11

11

0

4094

1

1

...

11

11

1

4095

F24

F23

..........

F14

F13

(FRAC)*

0

0

..........

0

0

0

0

0

..........

0

1

1

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

..........

0

0

4092

1

1

..........

0

1

4093

1

1

..........

1

0

4094

1

1

.........

1

1

4095

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN

INTEGER WORD

FRAC MSB WORD

R1

RAMP ON

0

RAMP DISABLED

RAMP ENABLED

1

Figure 29. Register 5 (R5)

REGISTER 5

Control Bits

With Bits[C5:C1] set to 00101, Register R5 is programmed.

Figure 29 shows the input data format for programming this

register.

Reserved

Bits[DB31:DB30] are reserved and must be set as shown in

Figure 29.

Ramp On

When Bit DB29 is set to 1, the ramp is started. When Bit DB29

is set to 0, the ramp function is disabled.

In continuous ramp modes, the ramp stops when Bit DB29 is

set to 0. For applications that require the ramp to stop at the

initial frequency, a write to Register R6 is required prior to

disabling the ramp function. In single ramp modes, a write to

Register R6 is required prior to repeating the single ramp

function.

When using the TX_DATA pin to trigger the ramp off in

continuous ramp modes, the ramp stops at the initial frequency,

a write to Register R6 is not required. When using the TX_

DATA pin in single ramp modes, a write to Register R6 is not

required prior to repeating the single ramp function.

12-Bit Integer Value (INT)

These 12 bits (Bits[DB28:DB17]) set the INT value, which

determines the integer part of the RF division factor. This INT

value is used in Equation 5. See the RF Synthesis: a Worked

Example section for more information. All integer values from 75

to 4095 are allowed.

12-Bit MSB Fractional Value (FRAC)

Bits[DB16:DB5], together with Bits[DB17:DB5] (FRAC LSB

word) in Register R6, control what is loaded as the FRAC value

into the fractional interpolator. This FRAC value partially

determines the overall RF division factor. It is also used in

Equation 1. These 12 bits are the most significant bits (MSB) of

the 25-bit FRAC value, and Bits[DB17:DB5] (FRAC LSB word)

in Register R6 are the least significant bits (LSB). See the RF

Synthesis: a Worked Example section for more information.