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AM186EM-33VC/W 数据表(PDF) 86 Page - Advanced Micro Devices |
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AM186EM-33VC/W 数据表(HTML) 86 Page - Advanced Micro Devices |
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86 / 98 page ![]() 86 Am186/188EM and Am186/188EMLV Microcontrollers PRELIMINA R Y Clock Waveforms—Active Mode Clock Waveforms—Power-Save Mode X1 X2 CLKOUTB CLKOUTA (Active, F=000) 36 37 39 40 42 43 46 69 70 38 44 45 X1 CLKOUTA(a) X2 CLKOUTB(c) CLKOUTB(b) Notes: a The Clock Divisor Select (F2–F0) bits in the Power Save Control Register (PDCON) are set to 010 (divide by 4). b The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 1. c The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 0. |
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