ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E

Data Sheet

Rev. F | Page 14 of 28

NIC

1

RO

2

RE

3

DE

4

DI

5

GND

6

GND

7

14

13

A

12

B

11

Z

10

Y

9

NIC

8

NIC = NO INTERNAL CONNECTION. THIS

PIN IS NOT INTERNALLY CONNECTED.

ADM3063E/

ADM3067E

TOP VIEW

(Not to Scale)

Figure 13. ADM3063E/ADM3067E 14-Lead SOIC Pin Configuration

Table 9. ADM3063E/ADM3067E Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 8

NIC

No Internal Connection. This pin is not internally connected.

2

RO

Receiver Output Data. This output is high when (A − B) ≥ −30 mV and is low when (A − B) ≤ −200 mV. This output is

tristated when the receiver is disabled; that is, when RE is driven high.

3

RE

Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high

disables the receiver.

4

DE

Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver

output into a high impedance state.

5

DI

Transmit Data Input. Data to be transmitted by the driver is applied to this input.

6, 7

GND

Ground.

9

Y

impedance state to avoid overloading the bus.

10

Z

impedance state to avoid overloading the bus.

11

B

Inverting Receiver Input.

12

A

Noninverting Receiver Input.

13, 14

recommended.