Data Sheet

ADP1071-1/ADP1071-2

Rev. B | Page 11 of 27

18

18

OVP

Output Overvoltage Protection. The OVP threshold is set at 1.36 V. Connect a resistive divider

from the OVP pin to the output and AGND2.

19

19

VDD2

Input Supply on the Secondary Side. Connect VDD2 to the output voltage of the power

supply for a self driven configuration. Connect a 4.7 µF capacitor from VDD2 to AGND2. The

size of this capacitor can be reduced if the input voltage to VDD2 is guaranteed to be stable.

20

20

VREG2

5 V Regulated LDO Output for Internal Bias and Powering of the Drivers of the Synchronous

Rectifiers. Do not use VREG2 as a reference or load. Connect a 1 µF capacitor from VREG2 to

AGND2.

21

21

AGND2

Analog Ground on Secondary Side.

22

22

NC

No Connect.

23

23

NC

No Connect.

24

24

SR

Driver Output for Synchronous Rectifier MOSFET.

EPAD1

Exposed Pad 1. Exposed pad is internally tied to AGND1.

EPAD2

Exposed Pad 2. Exposed pad is internally tied to AGND2.