ADP1071-2ACCZ-R7 datasheet(22/27 Pages) AD

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ADP1071-1/ADP1071-2

Data Sheet

Rev. B | Page 22 of 27

VFB (1.2V)

SS2 (1.4V)

VDD2 UVLO

(3.5V)

VDD2

200ms HICCUP COUNTER

SS2

CAPACITOR

SS1

CAPACITOR

DEPENDS ON VDD2

CAPACITOR AND IDD2

CONSUMPTION

(5mA TYPICAL)

HANDOVER TIME FROM

PRIMARY TO SECONDARY

(128 ×

tS)

TIME

PWM SWITCHING

DEPENDS ON SYSTEM

BANDWIDTH

Figure 21. Remote Software Reset with 200 ms Hiccup

VFB = 1.2V

SS2 = 1.4V

DEPENDS ON

LOOP BANDWIDTH

TIME

VDD2

DEPENDS ON

LOOP BANDWIDTH

VDD2_UVLO

3.1V

Figure 22. Tracking with SS2 Pin

OCP COUNTER

During overload conditions when the peak sensed currents

exceed the OCP threshold voltage of 120 mV on the CS pin, the

ADP1071-1/ADP1071-2 immediately terminate the remainder

of the PWM pulse. If the peak sense current continues to exceed

the threshold every switching period for 1.5 ms, the system

enters hiccup mode, by which it shuts down for approximately

40 ms and then soft starts. During an exceeded overcurrent

situation, such as a dead short, it is likely that the programmed

slope compensation is not enough, and therefore, the system

enters subharmonic oscillation. If this is the case, the system

cannot enter hiccup mode because the OCP threshold is crossed

every alternate switching period, and the 1.5 ms hiccup counter

resets.

To prevent this scenario, the ADP1071-1/ADP1071-2 latch the

last known state, whereby if an OCP condition registered as a 1

in one switching period and as a 0 in the next switching period,

it is still counted as a 1. In this manner, the system can enter

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