• 12 •

start-up times experienced by these types of circuits, a mechanism has been built in to disable

the POR and hence speed up on-board test of the device. The setting of this mode requires

values are required minimum.

Once the override mode has been entered, the chip immediately stops being reset and

override mode is cleared by writing a logic 0 to bit TESTC. Re-entry into the override mode is

only possible after TESTC is set to logic 1. Setting TESTC to logic 0 during normal operation

has no effect except to prevent entry into the POR override mode.

Fig 5 POR override sequence.

3 Serial interface

The serial interface of

between MPU and it peripherals ——.a serial Data I/O line and a serial CLK line driven by

MPU.

The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when

the bus is idle.

‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the

message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is defined as the start condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop

HM8563