PIC18F25800TESLASHML datasheet(91/484 Pages) MICROCHIP

91 / 484 page

 2004 Microchip Technology Inc.

Preliminary

DS39637A-page 89

PIC18F2480/2580/4480/4580

5.4

Data Addressing Modes

While the program memory can be addressed in only

one way – through the program counter – information

in the data memory space can be addressed in several

ways. For most instructions, the addressing mode is

fixed. Other instructions may use up to three modes,

depending on which operands are used and whether or

not the extended instruction set is enabled.

The addressing modes are:

• Inherent

• Literal

•Direct

•Indirect

An additional addressing mode, Indexed Literal Offset,

is available when the extended instruction set is

enabled (XINST configuration bit = 1). Its operation is

discussed in greater detail in Section 5.6.1 “Indexed

Addressing with Literal Offset”.

5.4.1

INHERENT AND LITERAL

ADDRESSING

Many PIC18 control instructions do not need any

argument at all; they either perform an operation that

globally affects the device or they operate implicitly on

one register. This addressing mode is known as

Inherent Addressing. Examples include SLEEP, RESET

and DAW.

Other instructions work in a similar way but require an

additional explicit argument in the opcode. This is

known as Literal Addressing mode because they

require some literal value as an argument. Examples

include ADDLW and MOVLW which, respectively, add or

move a literal value to the W register. Other examples

include CALL and GOTO, which include a 20-bit

program memory address.

5.4.2

DIRECT ADDRESSING

Direct addressing specifies all or part of the source

and/or destination address of the operation within the

opcode itself. The options are specified by the

arguments accompanying the instruction.

In the core PIC18 instruction set, bit-oriented and

byte-oriented instructions use some version of direct

addressing by default. All of these instructions include

some 8-bit literal address as their Least Significant

Byte. This address specifies either a register address in

one of the banks of data RAM (Section 5.3.3 “General

Purpose Register File”) or a location in the Access

Bank (Section 5.3.2 “Access Bank”) as the data

source for the instruction.

The Access RAM bit ‘a’ determines how the address is

interpreted. When ‘a’ is ‘1’, the contents of the BSR

(Section 5.3.1 “Bank Select Register (BSR)”) are

used with the address to determine the complete 12-bit

address of the register. When ‘a’ is ‘0’, the address is

interpreted as being a register in the Access Bank.

Addressing that uses the Access RAM is sometimes

also known as Direct Forced Addressing mode.

A few instructions, such as MOVFF, include the entire

12-bit address (either source or destination) in their

opcodes. In these cases, the BSR is ignored entirely.

The destination of the operation’s results is determined

by the destination bit ‘d’. When ‘d’ is ‘1’, the results are

stored back in the source register, overwriting its origi-

nal contents. When ‘d’ is ‘0’, the results are stored in

the W register. Instructions without the ‘d’ argument

have a destination that is implicit in the instruction; their

destination is either the target register being operated

on or the W register.

5.4.3

INDIRECT ADDRESSING

Indirect addressing allows the user to access a location

in data memory without giving a fixed address in the

instruction. This is done by using File Select Registers

(FSRs) as pointers to the locations to be read or written

to. Since the FSRs are themselves located in RAM as

Special File Registers, they can also be directly manip-

ulated under program control. This makes FSRs very

useful in implementing data structures, such as tables

and arrays in data memory.

The registers for indirect addressing are also imple-

mented with Indirect File Operands (INDFs) that permit

automatic manipulation of the pointer value with

auto-incrementing, auto-decrementing or offsetting

with another value. This allows for efficient code, using

loops, such as the example of clearing an entire RAM

bank in Example 5-5.

EXAMPLE 5-5:

HOW TO CLEAR RAM

(BANK 1) USING

INDIRECT ADDRESSING

Note:

The execution of some instructions in the

core PIC18 instruction set are changed

when the PIC18 extended instruction

set is enabled. See Section 5.6 “Data

Memory and the Extended Instruction

Set” for more information.

LFSR

FSR0, 100h

;

CLRF

POSTINC0

; Clear INDF

; register then

; inc pointer

BTFSS

FSR0H,1

; All done with

; Bank1?

BRA

; NO, clear next

CONTINUE

; YES, continue

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