WM8802SCFTV datasheet(20/65 Pages) WOLFSON

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WM8802

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PP Rev 1.1 April 2004

CLOCK SWITCH TRANSITION SIGNAL OUTPUT ( CKST )

CKST outputs Low when the output clock changes during PLL lock/unlock.

In the lock-in stage (PLL locked following the detection of input data) the CKST Low pulse falls at

the word clock edge generated from the XIN clock. The CKST Low pulse rises at the same timing as

RERR following the lapse of a given period.

In the unlock stage, the CKST Low pulse falls at the same timing as the PLL lock detection signal

RERR and rises following a given number of word clocks generated from the XIN clock.

The PLL lock status change and clock change timing is detected by the rising and falling edges of

the CKST Low pulse.

RERR

RMCK

VCO Clock

XTAL Clock

Locked status

RX0 to RX6

(a) Lock-in stage

45 ms to 300 ms

Same timing as

RERR

After PLL lock

Digital Data

Lock

Unlock

CKST

RERR

RMCK

VCO Clock

XTAL Clock

Locked status

RX0 to RX6

(b) Unlock stage

Same timing as RERR

Digital Data

Unlock

Lock

CKST

0.6 ms to 6.4 ms

Figure 8 Clock Switch Timing

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