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AX88655P 数据表(PDF) 9 Page - ASIX Electronics Corporation |
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AX88655P 数据表(HTML) 9 Page - ASIX Electronics Corporation |
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9 / 40 page ![]() ASIX ELECTRONICS CORPORATION 9 AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 2.1.2 GMII Interface Port 1 Signal Name I/O Pin No. Description GTX_CLK1 O 57 125MHz Clock Output: Please references section 2.1.1. TX_EN1 O 68 Transmit Enable: Please references section 2.1.1. TXD1[7:0] O 67 – 60 Transmit Data: Please references section 2.1.1. TX_CLK1 I/PD 59 MII Transmit Clock Input: Please references section 2.1.1. COL1 I/PD 45 Collision Detect: Please references section 2.1.1. CRS1 I/PD 44 Carrier Sense: Please references section 2.1.1. RX_DV1 I 55 Receive Data Valid: Please references section 2.1.1. RX_CLK1 I 54 Receive Clock Input: Please references section 2.1.1. RXD1[7:0] I/PD 53 - 46 Receive Data: Please references section 2.1.1. 2.1.3 GMII Interface Port 2 Signal Name I/O Pin No. Description GTX_CLK2 O 84 125MHz Clock Output: Please references section 2.1.1. TX_EN2 O 95 Transmit Enable: Please references section 2.1.1. TXD2[7:0] O 94 – 87 Transmit Data: Please references section 2.1.1. TX_CLK2 I/PD 86 MII Transmit Clock Input: Please references section 2.1.1. COL2 I/PD 72 Collision Detect: Please references section 2.1.1. CRS2 I/PD 71 Carrier Sense: Please references section 2.1.1. RX_DV2 I 82 Receive Data Valid: Please references section 2.1.1. RX_CLK2 I 81 Receive Clock Input: Please references section 2.1.1. RXD2[7:0] I/PD 80 - 73 Receive Data: Please references section 2.1.1. 2.1.4 GMII Interface Port 3 Signal Name I/O Pin No. Description GTX_CLK3 O 111 125MHz Clock Output: Please references section 2.1.1. TX_EN3 O 122 Transmit Enable: Please references section 2.1.1. TXD3[7:0] O 121 – 114 Transmit Data: Please references section 2.1.1. TX_CLK3 I/PD 113 MII Transmit Clock Input: Please references section 2.1.1. COL3 I/PD 99 Collision Detect: Please references section 2.1.1. CRS3 I/PD 98 Carrier Sense: Please references section 2.1.1. RX_DV3 I 109 Receive Data Valid: Please references section 2.1.1. RX_CLK3 I 108 Receive Clock Input: Please references section 2.1.1. RXD3[7:0] I/PD 107 - 100 Receive Data: Please references section 2.1.1. |
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