Revision 1.1
-7-
2001/8/21
MTV038
(Revision 1.1)
MYSON
TECHNOLOGY
acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calcu-
lated with the following equation,
For CRT:
Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width
Where P = One pixel display time = One horizontal line display time / (HORR*12)
For LCD:
Horizontal delay time = ( HORD * 6 + 49) * P
Where P = 1 XIN pixel display time
3.5 Phase lock loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution reg-
ister (HORR). The frequency of VCLK is determined by the following equation:
VCLK Freq = HFLB Freq * HORR * 12
The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB input
is not present to MTV038, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in
oscillator to ensure data integrity.
3.6 Display & Row control registers
The internal RAM contains display and row control registers. The display registers have 450 locations which
are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each dis-
play register has its corresponding character address on ADDRESS byte, its corresponding background color,
button box format, 1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is
allocated at column 30 for row 0 to row 14 of attribute bytes, it is used to select background color or button box
and set character size to each respective row. If double width character is chosen, only even column charac-
ters could be displayed on screen and the odd column characters will be hidden.
FIGURE 4. Address Bytes of Display Registers Memory Map
ROW #
COLUMN #
0 1
28 29
30
31
0
1
13
14
CHARACTER ADDRESS BYTES
of DISPLAY REGISTERS
ROW
ATTRIBUTE
CRTL REG
R
E
S
E
R
V
E
D
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