CS61318-IP datasheet(12/28 Pages) CIRRUS

12 / 28 page

CS61318

DS441PP2

An address/command byte, shown in Figure 9,

points to addresses 0x10 through 0x14 (address

0x10 shown), and precedes a data byte. The first bit

of the address/command byte determines whether a

read or a write is requested. The next six bits con-

tain the address. The last bit is ignored. Data to the

internal registers is input on the eight clock cycles

immediately following the address/command byte.

SCLK

SDO

CLKE = 0

SDI

Address/Command Byte

Data Input/Output

R/W

Figure 9. Input/Output Timing (showing address 0x10)

Note: All Control Registers initialize to 0x00.

432

ADDR

Control Register 1

TAOS

LLOOP

RLOOP

Reserved

Set to “0”

Reserved

Set to “0”

HDB3

NLOOP

LOS

0x10 R/W

Control Register 2

AIS

RAMPLSE

Reserved

set to ‘0”

LOOPDN

LOOPUP

RPWDN

TxHIZ

Reserved

set to ‘0”

0x11 R/W

Equalizer Gain

(EQGAIN)

EQ4

EQ3

EQ2

EQ1

EQ0

0x12 R

Arbitrary Waveform RAM

Address

MSB

LSB

0x13 R/W

Reserved

Set to “0”

0x14

Table 2. Register Map

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