LM2502 datasheet(21/27 Pages) NSC

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LM2502 Features and Operation

(Continued)

between 3 and 25 MHz. See Table 10 below, Multiplier/

Divisor times CLK rate must also be less than 76.8 MHz. The

76.8 MHz limitation is based on the semiconductor process

used on this implementation — it is not an MPL limitation.

Line rate should also be selected such that it is faster than

the input load rate when bursting data across the link. Oth-

erwise 8/10 X Line rate must be greater than the input load

rate to the Master. At the maximum raw data rate of 307

Mbps, the maximum information rate is 245 Mbps. Thus the

parallel load rate at the Master input must not exceed 15.4

Mega Transfers per second sustained (of 16 data bits). The

Master can accommodate up to four words at a higher rate

due to internal FIFOs.

Configuration pins (PLL_CON[2:0], and M/S*) are used to

determine the mode of which the part is operating in. In the

Slave configuration the PLL block is disabled. The Slave

PLL_CON pins are required to set up the proper divisor for

the CLK pin. Slave PLL_CON[2:0] pins do not need to be set

the same as the Master, this allows for clock multiplication /

division to be supported for the output clock reference signal.

RESET

On both the Master and the Slave, the PD* pin resets the

logic. The PD* pins should be held low until the power supply

has ramped up and is stable and within specifications. The

Slave PD* pin should be driven High first or at the same time

as the Master. This will ensure that the Slave sees the start

up sequence from the Master.

MASTER/SLAVE SELECTION

The M/S* pin is used to configure the device as either a

Master or Slave device. When the M/S* pin is a Logic High,

the Master configuration is selected. The Driver block is

enabled for the MC line, and the MD lines. When the M/S*

pin is a Logic Low, the Slave configuration is selected. The

Receiver block is enabled for the MC line, and the MD lines.

TABLE 10. PLL_CON Settings

PLLCON2

PLLCON1

PLLCON0

Multiplier

(Master)

MC out

Divisor

(Slave)

CLKout

Minimum

CLK Input

Maximum

CLK Input

(MC % 76.8

MHz)

CLK X 2

MC / 2

13 MHz

25 MHz

CLK X 4

MC / 4

6 MHz

19.2 MHz

CLK X 6

MC / 6

3 MHz

12.8 MHz

CLK X 7

MC / 7

3 MHz

10.97 MHz

CLK X 8

MC / 8

3 MHz

9.60 MHz

CLK X 9

MC / 9

3 MHz

8.53 MHz

CLK X 10

MC / 10

3 MHz

7.68 MHz

(Reserved)

Application Information

SYSTEM CONSIDERATIONS

When employing the MPL SERDES chipset in place of a

parallel bus, a few system considerations must be taken into

account. Before sending commands (ie initialization com-

mands) to the display, the SERDES must be ready to trans-

mit data across the link. The MPL link must be powered up,

and the PLL must be locked. Also a review of the Slave

output timing should be completed to insure that the timing

parameters provided by the Slave output meet the require-

ments of the LCD driver input. Specifically, pulse width on

CSn*, RD* / WR*, data valid time, and bus cycle rate should

be reviewed and checked for inter-operability. Additional de-

tails are provided next:

The MPL link should be started up as follows: The chipset

should be powered up first, V

DDIO should not be powered up

first, it may be at the same time as V

DD/VDDA or lag. During

power up, the PD* inputs should be held LOW and released

once power is stable and within specification. The Slave PD*

may be released first or at the same time as the Master. CLK

should be applied prior to releasing PD*.

Before data can be sent across the MPL serial link, the link

must be ready for transmission. The CLK needs to be ap-

plied to the device, and the PLL locked. This is controlled by

a keep-off counter set for 4096 cycles. After the PLL has lock

and the counter expired, an additional 40 clock cycles are

required for the calibration of the MPL link. After this, data

may now be written to the device.

It takes 5MC Cycles to send a 16-bit CPU Write including the

serial overhead. The MC cycle time is calculated based on

the PLL_CON[2:0] setting and also the input clock fre-

quency. For example, a 19.2MHz input CLK and a 4X

PLLCON setting yields a MC frequency of 76.8MHz. Thus it

takes 65.1ns to send the word in serial form. To allow some

idle time between transmissions (this will force a bit sync per

word if the gap is long enough in between), the load rate on

the Master input should not be faster than 6MC cycles, or

every 78ns in our example to support a data pipe line. This is

sometimes referred to as the bus cycle time (time between

commands).

The Slave output times is also a function of MC cycles. Note

that in i80 mode, the width of the WR* pulse (in m68 mode

the width of the CS*) pulse low is three MC cycles regard-

less of the pulse width applied to the Master input. System

designers need to check compatibility with the display driver

to ensure this pulse width meets its requirement. If it is too

fast, select a lower PLLCON setting or apply a slower input

clock.

The CLK input must be free running and not gapped. If the

clock is stopped a RESET (PD* = Low) cycle should be done

and the link brought up again.

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