LNBEH21

14/22

THERMAL DESIGN NOTES

During normal operation, this device dissipates some power. The power dissipation depends on the

selected communication mode (DiSEqC or 13/18 control word communication).

When the device is used in DiSEqC mode, at maximum rated output current (750mA), the voltage drop on

the linear regulator lead to a total dissipated power that is about 1.65W.

If the control word communication mode is selected, at maximum rated current of 450mA, the total power

dissipated is about 1W. By the way, during the 13/18V pulses code transmission (OM=VOM=1) the

average power dissipation is higher than 1W because, in this case, before to start sending the 13/18V

between 13V and 18V; this means that, in the 13V half period the peak of power dissipation is about 3.8W

typ. (@ Iout=450mA max.). Obviously this is the peak power dissipation as the average value during the

code transmission has to be calculated taking into account the 0/1 bits combination.

The heat generated requires a suitable heatsink to keep the junction temperature below the

overtemperature protection threshold. Assuming a 45°C temperature inside the Set-Top-Box case and a

While this can be easily achieved using a through-hole power package that can be attached to a small

heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB

solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous

copper area of the pcb ground layer to dissipate the heat coming from the IC body by mean the ground

exposed pad present on the bottom side of the PSO-20 package.

be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the

opposite side where the IC is placed. In figure 9, is shown a suggested layout for the PSO-20 package

with a dual layer PCB, where the IC exposed pad connected to GND and the square dissipating area are

thermally connected through 32 vias holes, filled by solder. This arrangement, when L=25mm, achieves

Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground

exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to

design a dissipating area having a shape as square as possible and not interrupted by other copper

traces.

Figure 9: PowerSO-20 Suggested Pcb Heatsink Layout