3

All data sheets are subject to change without notice

©2005 Maxwell Technologies

All rights reserved.

16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

21

BUSY

Busy Output. Falls when a conversion is started, and remains LOW until the conversion is com-

pleted and the data is latched into the output shift register. CS or R/C must be HIGH when

BUSY rises, or another conversion will start without time for signal acquisition.

22

PWRD

Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly

reduced. Results from the previous conversions are maintained in the output shift register.

23

LPVANA

Latchup Protection Analog Supply.

24

LPVDIG

Latchup Protection Digital Supply.

Analog Inputs

R1

IN

R2

IN

R3

IN

CAP

1. Indefinite short to AGND2, momentarily short to V

-25

-25

-25

V

25

25

25

AGND2 - 0.3

V

V

V

V

Ground Voltage Differences: DGND, AGND2

-0.3

0.3

V

V

ANA

--

7

V

V

DIG

7V

V

--

0.3

V

Specified Performance

-40

85

Digital Inputs

-0.3

V

V

Storage Temperature

T

STG

-65

150

Integral Linearity Error

-40 to 85°C

--

--

--

--

±3

±5

Differential Linearity Error

-40 to 85°C

--

--

--

--

-2, 3

-1, 6

LSB

LSB

15

--

--

Bits

--

1.3

--

LSB

--

--

±0.6

%

±0.6

%

Full Scale Error Drift

--

±7

--