AD7940

Rev. 0 | Page 5 of 20

TIMING SPECIFICATIONS

a voltage level of 1.6 V.

Table 3.

Parameter

3 V

5 V

Unit

Description

fSCLK1

250

250

kHz min

2.5

2.5

MHz max

min

50

50

ns min

Minimum quiet time required between bus relinquish and start of

next conversion

10

10

ns min

Minimum CS pulse width

10

10

ns min

CS to SCLK setup time

48

35

ns max

Delay from CS until SDATA three-state disabled

120

80

ns max

Data access time after SCLK falling edge

ns min

SCLK low pulse width

ns min

SCLK high pulse width

10

10

ns min

SCLK to data valid hold time

45

35

ns max

SCLK falling edge to SDATA high impedance

1

1

µs typ

Power up time from full power-down

and defined as the time required for the output to cross 0.8 V or 2.0 V.

Figure 2

Figure 2.

The measured number is then extrapolated

time of the part and is independent of the bus loading.

section.

Power vs. Throughput Rate

200

µAI

OL

200

µAI

OH

1.6V

TO OUTPUT

PIN

50pF

Figure 2. Load Circuit for Digital Output Timing Specification