Philips Semiconductors

Product data sheet

PCA9544A

2004 Sep 29

13

AC CHARACTERISTICS

SYMBOL

PARAMETER

STANDARD-MODE

FAST-MODE

UNIT

MIN

MAX

MIN

MAX

—

—

ns

SCL clock frequency

0

100

0

400

kHz

Bus free time between a STOP and START condition

4.7

—

1.3

—

µs

Hold time (repeated) START condition

After this period, the first clock pulse is generated

4.0

—

0.6

—

µs

LOW period of the SCL clock

4.7

—

1.3

—

µs

HIGH period of the SCL clock

4.0

—

0.6

—

µs

Set-up time for a repeated START condition

4.7

—

0.6

—

µs

Set-up time for STOP condition

4.0

—

0.6

—

µs

Data hold time

3.45

0.9

µs

Data set-up time

250

—

100

—

ns

Rise time of both SDA and SCL signals

—

1000

300

ns

Fall time of both SDA and SCL signals

—

300

300

µs

Capacitive load for each bus line

—

400

—

400

µs

Pulse width of spikes which must be suppressed

by the input filter

—

50

—

50

ns

—

1

—

1

µs

—

0.6

—

0.6

µs

Data valid Acknowledge

—

1

—

1

µs

INT

—

4

—

4

µs

—

2

—

2

µs

10

—

1

—

ns

500

—

500

—

ns

NOTES:

1. Pass gate propagation delay is calculated from the 20

the undefined region of the falling edge of SCL.

4. Measurements taken with 1 k

Ω pull-up resistor and 50 pF load.

P

P

S

Sr

SDA

SCL

SU00645