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LT1815

LT1816/LT1817

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APPLICATIO S I FOR ATIO

Layout and Passive Components

As with all high speed amplifiers, the LT1815/LT1816/

LT1817 require some attention to board layout. A ground

plane is recommended and trace lengths should be mini-

mized, especially on the negative input lead.

Low ESL/ESR bypass capacitors should be placed directly

at the positive and negative supply (0.01

µF ceramics are

recommended). For high drive current applications, addi-

tional 1

µF to 10µF tantalums should be added.

The parallel combination of the feedback resistor and gain

setting resistor on the inverting input combine with the

input capacitance to form a pole that can cause peaking or

even oscillations. If feedback resistors greater than 1k are

used, a parallel capacitor of value:

should be used to cancel the input pole and optimize

dynamic performance. For applications where the DC

be an I-to-V converter.

Input Considerations

The inputs of the LT1815/LT1816/LT1817 amplifiers are

connected to the base of an NPN and PNP bipolar transis-

tor in parallel. The base currents are of opposite polarity

and provide first-order bias current cancellation. Due to

variation in the matching of NPN and PNP beta, the

polarity of the input bias current can be positive or

negative. The offset current, however, does not depend

on beta matching and is tightly controlled. Therefore, the

use of balanced source resistance at each input is recom-

mended for applications where DC accuracy must be

maximized. For example, with a 100

Ω source resistance

at each input, the 800nA maximum offset current results

in only 80

µV of extra offset, while without balance the 8µA

maximum input bias current could result in a 0.8mV offset

contribution.

The inputs can withstand differential input voltages of up

to 6V without damage and without needing clamping or

series resistance for protection. This differential input

voltage generates a large internal current (up to 80mA),

which results in the high slew rate. In normal transient

closed-loop operation, this does not increase power

dissipation significantly because of the low duty cycle of

the transient inputs. Sustained differential inputs, how-

ever, will result in excessive power dissipation and there-

fore this device should not be used as a comparator

.

Capacitive Loading

The LT1815/LT1816/LT1817 are optimized for high band-

width and low distortion applications. They can drive a

capacitive load of 10pF in a unity-gain configuration and

more with higher gain. When driving a larger capacitive

load, a resistor of 10

Ω to 50Ω should be connected

between the output and the capacitive load to avoid ringing

or oscillation. The feedback should still be taken from the

output so that the resistor will isolate the capacitive load

to ensure stability.

Slew Rate

The slew rate of the LT1815/LT1816/LT1817 is proportional

to the differential input voltage. Therefore, highest slew rates

are seen in the lowest gain configurations. For example, a

5V output step in a gain of 10 has a 0.5V input step, whereas

in unity gain there is a 5V input step. The LT1815/LT1816/

LT1817 are tested for a slew rate in a gain of – 1. Lower

slew rates occur in higher gain configurations.

Programmable Supply Current

(LT1815/LT1816A)

In order to operate the LT1815S6 or LT1816A at full speed

negative supply through a resistance of 75

Ω or less.

To adjust or program the supply current and speed of the

Figure 1. The amplifiers are fully functional with 0

≤ 40k. Figures 2 and 3 show how the gain bandwidth and

supply current vary with the value of the programming

section of the data sheet specifies maximum supply

current and offset voltage, as well as minimum gain

of 40k.