LT1817CS datasheet(13/20 Pages) LINER

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LT1815

LT1816/LT1817

181567fa

APPLICATIO S I FOR ATIO

ISET

V–

181567 F01

V+

RSET

–5V

–

LT1815S6

Figure 1. Programming Resistor Between ISET and V–

RSET PROGRAMING RESISTOR (Ω)

100

150

200

250

10k

40k

181567 F02

100

VS = ±5V

TA = 25°C

RL = 500Ω

RL = 100Ω

Figure 2. Gain Bandwidth Product vs RSET Programming Resistor

RSET PROGRAMMING RESISTOR (Ω)

10k

40k

181567 F03

100

VS = ±5V

TA = 25°C

PER AMPLIFIER

Figure 3. Supply Current vs RSET Programming Resistor

Power Dissipation

The LT1815/LT1816/LT1817 combine high speed and

large output drive in small packages. It is possible to

exceed the maximum junction temperature specification

(150

°C)undercertainconditions.Maximumjunctiontem-

perature (TJ) is calculated from the ambient temperature

(TA), power dissipation per amplifier (PD) and number of

amplifiers (n) as follows:

TJ = TA + (n • PD • θJA)

Power dissipation is composed of two parts. The first is

due to the quiescent supply current and the second is due

to on-chip dissipation caused by the load current. The worst-

case load induced power occurs when the output voltage

is at 1/2 of either supply voltage (or the maximum swing

if less than 1/2 the supply voltage). Therefore PDMAX is:

PDMAX = (V+ – V–) • (ISMAX) + (V+/2)2/RL or

PDMAX = (V+ – V–) • (ISMAX) + (V+ – VOMAX) •

(VOMAX/RL)

Example: LT1816IS8 at 85

°C, VS = ±5V, RL=100Ω

PDMAX = (10V) • (11.5mA) + (2.5V)2/100Ω = 178mW

TJMAX = 85°C + (2 • 178mW) • (150°C/W) = 138°C

Circuit Operation

The LT1815/LT1816/LT1817 circuit topology is a true

voltage feedback amplifier that has the slewing behavior of

a current feedback amplifier. The operation of the circuit

can be understood by referring to the Simplified Sche-

matic. Complementary NPN and PNP emitter followers

buffer the inputs and drive an internal resistor. The input

voltage appears across the resistor, generating current

that is mirrored into the high impedance node.

Complementary followers form an output stage that buff-

ers the gain node from the load. The input resistor, input

stage transconductance and the capacitor on the high

impedance node determine the bandwidth. The slew rate

is determined by the current available to charge the gain

node capacitance. This current is the differential input

voltage divided by R1, so the slew rate is proportional to

the input step. Highest slew rates are therefore seen in the

lowest gain configurations.

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