LTC6900

6

6900f

THEORY OF OPERATIO

As shown in the Block Diagram, the LTC6900’s master

oscillator is controlled by the ratio of the voltage between

SET pin. The voltage on the SET pin is forced to approxi-

bias voltage. This voltage is accurate to

±8%ataparticular

input current and supply voltage (see Figure 1).

variation. This provides the LTC6900’s high precision. The

master oscillation frequency reduces to:

ƒ=

Ω









MO

SET

MHz

k

R

10

20

•

The LTC6900 is optimized for use with resistors between

10k and 2M, corresponding to master oscillator frequen-

cies between 100kHz and 20MHz.

To extend the output frequency range, the master oscilla-

tor signal may be divided by 1, 10 or 100 before driving

OUT (Pin 5). The divide-by value is determined by the state

of the DIV input (Pin 4). Tie DIV to GND or drive it below

DESIRED OUTPUT FREQUENCY (Hz)

10

100

1k

100k

1M

10M

6900 F02

1

10k

10000

1000

100M

÷100

÷10

÷1

0.5V to select

÷1. This is the highest frequency range, with

the master output frequency passed directly to OUT. The

DIV pin may be floated or driven to midsupply to select

÷10, the intermediate frequency range. The lowest fre-

quency range,

including the overlapping frequency ranges near 100kHz

and 1MHz.

The CMOS output driver has an on resistance that is

typically less than 100

Ω. In the ÷1 (high frequency) mode,

the rise and fall times are typically 7ns with a 5V supply and

11ns with a 3V supply. These times maintain a clean

square wave at 10MHz (20MHz at 5V supply). In the

÷10

and

÷100 modes, where the output frequency is much

lower, slew rate control circuitry in the output driver

increases the rise/fall times to typically 14ns for a 5V

supply and 19ns for a 3V supply. The reduced slew rate

lowers EMI (electromagnetic interference) and supply

bounce.

1

0.1

0.8

1.2

1.3

1.4

10

100

1000

6900 F01

1.1

1.0

0.9