LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB design:

Signal Integrity and Termination

Considerations

- Keep traces short!

- Trace = Inductor. With a capacitive load this equals ringing!

- Long trace = Transmission Line. Without proper termination

this will cause reflections ( looks like ringing ).

- Design long traces as “striplines” or “microstrips” with

defined impedance.

- Match trace at one side to avoid reflections bouncing back

and forth.

Decoupling and Power Supply

Considerations

- Place decoupling capacitors as close as possible to the

VDD pin(s) to limit noise from the power supply

- Multiple VDD pins should be decoupled separately for

best performance.

- Addition of a ferrite bead in series with VDD can help

prevent noise from other board sources

- Value of decoupling capacitor is frequency dependant.

Typical values to use are 0.1

? F for designs using crystals <

50MHz and 0.01

? F for designs using crystals > 50MHz.

Typical CMOS termination

Place Series Resistor as close as possible to CMOS output

CMOS Output Buffer

( Typical buffer impedance 20

To CMOS Input

Series Resistor

Use value to match output

buffer impedance to 50

trace. Typical value 30

50

line

Series and parallel capacitors used to fine tune the crystal load to the circuit load.

– Series Capacitor, used to lower circuit load to match crystal load. Raises frequency

offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the

oscillator.

– Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers

frequency offset.

Crystal

XIN

8

1

XOUT

Cpt

Cpt

Cst

1.8V-3.3V, 5MHz to 60MHz XO IC

ABX1027

HIGH PERFORMANCE GENERAL PURPOSE OSCILLATOR IC

ABRACON IS

ISO 9001 / QS 9000

CERTIFIED

ABRACON IS

ISO 9001 / QS 9000

CERTIFIED

30332 Esperanza, Rancho Santa Margarita, California 92688

Revised: 08.14.07

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