UPD72012 datasheet(5/36 Pages) NEC

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Data Sheet S13918EJ3V0DS

µPD72012

PIN NAME

AGND1

: Analog GND1 (Xtal)

AGND2

: Analog GND2 (DPLL)

AVDD1

: Analog VDD1 (Xtal)

AVDD2

: Analog VDD2 (DPLL)

CLKSEL

: Clock Frequency Control

CLK/X2

: 48 MHz OSC, 4 MHz Xtal

Clock Input

CS1

: Over Current Detect #1

CS2

: Over Current Detect #2

CS3

: Over Current Detect #3

CS4

: Over Current Detect #4

CS5

: Over Current Detect #5

D10

: Downstream Port #1 D+

D11

: Downstream Port #1 D–

D20

: Downstream Port #2 D+

D21

: Downstream Port #2 D–

D30

: Downstream Port #3 D+

D31

: Downstream Port #3 D–

D40

: Downstream Port #4 D+

D41

: Downstream Port #4 D–

D50

: Downstream Port #5 D+

D51

: Downstream Port #5 D–

DGND

: Digital GND

DGND (Buffer)

: Digital GND (Buffer)

DVDD

: Digital VDD

DVDD (Buffer)

: Digital VDD (Buffer)

OSL

: OSC Suspend Output

PP1

: Port Power Control #1

PP2

: Port Power Control #2

PP3

: Port Power Control #3

PP4

: Port Power Control #4

PP5

: Port Power Control #5

PSSEL

: Powered Mode Control

PVSEL

: Down Port Value Control

RST

: Reset

UD0

: Root Port #0 D+

UD1

: Root Port #0 D–

: 4 MHz Xtal Clock Input

UPD72012 数据表(PDF) 5 Page - NEC

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