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STM32MP157DAC1 数据表(PDF) 132 Page - STMicroelectronics |
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STM32MP157DAC1 数据表(HTML) 132 Page - STMicroelectronics |
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132 / 258 page  Electrical characteristics STM32MP157A 132/258 DS12504 Rev 2 VAVM_0 Analog voltage (VDDA) detector threshold 0 Rising edge 1.655 1.7 1.745 V Falling edge 1.555 1.6 1.645 VAVM_1 Analog voltage (VDDA) detector threshold 1 Rising edge 2.055 2.1 2.145 V Falling edge 1.955 2 2.045 VAVM_2 Analog voltage (VDDA) detector threshold 2 Rising edge 2.455 2.5 2.545 V Falling edge 2.355 2.4 2.445 VAVM_3 Analog voltage (VDDA) detector threshold 3 Rising edge 2.755 2.8 2.845 V Falling edge 2.655 2.7 2.745 Vhyst_VDDA Hysteresis of analog voltage (VDDA) detector - - 100 - mV IVDD_AVM(1) Analog Voltage Monitoring (VDDA) consumption on VDD -- - 0.248 µA IVDDA_AVM(1) Analog Voltage Monitoring (VDDA) consumption on VDDA Resistor bridge - 2.12 - µA VPVDCORE_0(4) Digital core domain supply voltage (VDDCORE) detector threshold 0 (Run) Rising edge 0.95 0.995 1.04 V Falling edge 0.91 0.955 1 VPVDCORE_1(5) Digital core domain supply voltage (VDDCORE) detector threshold 1 (LPLV_Stop) Falling edge 0.71 0.755 0.8 V Vhyst_VDDCORE Hysteresis of Digital core domain supply voltage (VDDCORE) detector - - 40 - mV tVDDCORETEMPO Tempo on VPVDCORE_0 at rising edge of VDDCORE to ensure that VDDCORE is fully established - 200 340 550 µs tSEL_VDDCORETE MPO Tempo on VPVDCORE_1 at rising edge of VDDCORE to ensure that VDDCORE is fully established on exit of LPLV-Stop mode - 234 380 606 µs IVDD_VDDCOREVM (1) VDDCORE Voltage Monitoring consumption on VDD - 1.7 2.6 4.2 µA USB_VTH USB Threshold voltage - - 1.21 - V 1. Guaranteed by design. 2. No hysteresis when using PVD_IN pin. 3. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables. 4. During the first rising edge of VDDCORE, the slope should be less than 2 ms/V to ensure VDDCORE is fully established before the end of the tVDDCORETEMPO. 5. When exiting from LPLV-STOP mode to RUN mode the rising slope for VDDCORE should be less than 1 ms/V to ensure VDDCORE is fully established before the end of the tVDDCORETEMPO. Table 15. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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