STM32MP157DAC1 datasheet(129/258 Pages) STMICROELECTRONICS

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DS12504 Rev 2

129/258

STM32MP157A

Electrical characteristics

238

6.3.1

General operating conditions

6.3.2

Operating conditions at power-up / power-down

Subject to general operating conditions.

2. Min VDD is 2.25 V when REG1V8 is used BYPASS_REG1V8 = 0.

3. Should be connected to same power supply voltage as VDD.

4. It is recommended to connect VDD_PLL and VDD_PLL2 to same power supply as VDD.

5. 1.25 V is the max allowed voltage, however LPLV-Stop mode is only relevant for VDDCORE up to 0.95 V. In LPLV-Stop

mode, if VDDQ_DDR is not shutdown, to avoid overconsumption on VDDQ_DDR, the DDR memory must be put in

SelfRefresh and DDR PHY must be set in retention mode (setting bit DDRRETEN: DDR retention enable of PWR control

6. DAC cannot be used with VREF below 1.8 V.

7. ADC cannot be used with VREF below 2 V and VDDA above 2 V.

8. Depending on package selected, either VDD3V3_USBFS and VDD3V3_USBHS or only VDD3V3_USB are available.

9. For operation with voltage higher than Min (VDD, VDDA, VDD3V3_USBFS) +0.3 V, the internal Pull-up and Pull-Down resistors

must be disabled.

10. Independent from any other supply.

11. Min(VDD, VDDA, VDD3V3_USBFS) +3.6 V < 5.5 V. This formula has to be applied on power supplies related to the IO structure

described by the pin definition table.

Table 14. Operating conditions at power-up / power-down

Symbol

Parameter

Min

Max

Unit

tVDD(1)

1. VDD must be present before VDDCORE .

VDD rise time rate

∞

µs/V

VDD fall time rate

∞

tVDDA

VDDA rise time rate

∞

VDDA fall time rate

∞

tVDD3V3_USB(2)

tVDD3V3_USBHS

tVDD3V3_USBFS

2. VDDA1V8_REG must be present before VDD3V3_USBHS.

VDD3V3_USBxx rise time rate

∞

VDD3V3_USBxx fall time rate

∞

tVDDCORE

VDDCORE rise time rate (from

reset to RUN mode)

2000(3)

3. In case VDDCORE rise time is larger than 2 ms/V, user should control the NRST_CORE signal with a Power

Good (PG) control signal from the external regulator to avoid dysfunction of the device due to VDDCORE

potentially not yet established when internal reset signal is de-activated after tVDDCORETEMPO (cf.Table 14

and Figure 13).

VDDCORE rise time rate (from

LPLV-Stop to RUN mode)

1000(4)

4. In case VDDCORE rise time at exit of LPLV-Stop is larger than 1 ms/V, there is a risk of unwanted reset due

to VDDCORE potentially not yet established after tSEL_VDDCORETEMPO (cf.Table 14 and Figure 14). In such a

case, the VDDCORE supply should not be decreased during LPLV-Stop mode.

VDDCORE fall time rate

7.33

∞

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