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LFEC 数据表(PDF) 21 Page - Lattice Semiconductor |
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LFEC 数据表(HTML) 21 Page - Lattice Semiconductor |
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21 / 117 page  2-18 Architecture Lattice Semiconductor LatticeECP/EC Family Data Sheet Figure 2-21. MULTADDSUM Clock, Clock Enable and Reset Resources Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3) one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3) at each input register, pipeline register and output register. Signed and Unsigned with Different Widths The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36 width is reached. Table 2-8 provides an example of this. Multiplier Add/Sub0 x n m m+n (default) m+n (default) m+n+1 m+n+2 m+n+2 m+n+1 m+n (default) m+n (default) m n m n m n n m x n n m n n m Multiplier Multiplier Multiplier Add/Sub1 x n m m n m n m n n m x n m m n m n n m SUM Multiplier B0 Multiplicand A0 Multiplier B1 Multiplicand A1 Multiplier B2 Multiplicand A2 Multiplier B3 Multiplicand A3 Signed Shift Register B In Output Addn0 Pipeline Register CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Input Register Pipeline Register Input Register To Add/Sub0 To Add/Sub0, Add/Sub1 Pipeline Register Pipeline Register Input Register To Add/Sub1 Addn1 Pipeline Register Pipeline Register Pipeline Register Shift Register A In Shift Register B Out Shift Register A Out Input Data Register A Input Data Register A Input Data Register A Input Data Register A Input Data Register B Input Data Register B Input Data Register B Input Data Register B |
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