DSC6003JL1B-B datasheet(3/26 Pages) MICROCHIP

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DS20006133A-page 3

DSC60XXB

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Supply Voltage .......................................................................................................................................... –0.3V to +4.0V

Input Voltage (VIN) ..............................................................................................................................–0.3V to VDD+0.3V

ESD Protection ............................................................................................................ 4 kV HBM, 400V MM, 2 kV CDM

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, VDD = 1.8V –5% to 3.3V +10%, TA = –40°C to +125°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Supply Voltage Note 1

VDD

1.71

—

3.63

—

Active Supply Current

IDD

—1.3

—

FOUT = 24 MHz, VDD = 1.8V,

No Load

Power Supply Ramp

tPU

0.1

—

100

Note 9

Standby Supply Current

Note 2

ISTBY

—1.0

—

µA

VDD = 1.8/2.5V

—1.5

—

VDD = 3.3V

Frequency

0.002

—

MHz

—

Frequency Stability Note 3

∆f—

—

±20

±25

±50

ppm

All temp ranges

Aging

∆f

——

±5

ppm

1st year @25°C

—

±1

Per year after first year

Startup Time

tSU

——

1.5

From 90% VDD to valid clock

output, T = 25°C

Input Logic Levels

Note 4

VIH

0.7 x VDD

—

Input Logic High

VIL

—

0.3 x VDD

Input Logic Low

Output Disable Time

Note 5

tDA

——

200 +

2 Periods

—

Output Enable Time

Note 6

tEN

——

µs

—

Enable Pull-Up Resistor

Note 7

——

300

—

kΩ

If configured

Output Logic Levels,

Low Drive

VOH

0.8 x VDD

—

Output Logic High, I = 1 mA

VOL

—

0.2 x VDD

Output Logic Low, I = –1 mA

Note 1: Pin 4 VDD should be filtered with 0.1 µF capacitor.

2: Not including current through pull-up resistor on EN pin (if configured).

3: Includes frequency variations due to initial tolerance, temp. and power supply voltage.

4: Input waveform must be monotonic with rise/fall time < 10 ms

5: Output Disable time takes up to two periods of the output waveform + 200 ns.

6: For parts configured with OE, not Standby.

7: Output is enabled if pad is floated or not connected.

8: Output Duty Cycle will be 40% to 60% when output frequency is between 40 MHz to 60 MHz.

9: Time to reach 90% of target VDD. Power ramp rise must be monotonic.

10: Peak-to-peak period jitter is measured over 10,000 cycles.

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