PCF8811MUSLASH2DASLASH1 datasheet(21/73 Pages) PHILIPS

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2004 May 17

Philips Semiconductors

Product speciﬁcation

× 128 pixels matrix LCD driver

PCF8811

12 I2C-BUS INTERFACE

12.1

Characteristics of the I2C-bus (Hs-mode)

The I2C-bus Hs-mode is for bidirectional, two-line

communication between different ICs or modules with

speeds of up to 3.4 MHz. The only difference between

Hs-mode slave devices and F/S-mode slave devices is the

speed at which they operate, therefore the buffers on the

SCLH and SDAH have open-drain outputs. This is the

same for I2C-bus master devices which have an

open-drain SDAH output and a combination of an

open-drain, pull-down and current source pull-up circuits

on the SCLH output. Only the current source of one master

is enabled at any one time, and only during Hs-mode. Both

lines must be connected to a positive supply via a pull-up

resistor.

Data transfer may be initiated only when the bus is not

busy.

12.1.1

SYSTEM CONFIGURATION

The system configuration is illustrated in Fig.22.

Definitions of the I2C-bus terminology:

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from the

bus

• Master: the device which initiates a transfer, generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-master: more than one master can attempt to

control the bus at the same time without corrupting the

message

• Arbitration: procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

12.1.2

BIT TRANSFER

One data bit is transferred during each clock pulse (see

Fig.23). The data on the SDA line must remain stable

during the HIGH period of the clock pulse as changes in

the data line at this time will be interpreted as a control

signal.

12.1.3

START AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock

is HIGH is defined as the STOP condition (P). The START

and STOP conditions are illustrated in Fig.24.

12.1.4

ACKNOWLEDGE

Each byte of eight bits is followed by an acknowledge bit;

see Fig.25. The acknowledge bit is a HIGH signal put on

the bus by the transmitter during which time the master

generates an extra acknowledge-related clock pulse.

A slave receiver which is addressed must generate an

acknowledge after the reception of each byte. A master

receiver must also generate an acknowledge after the

reception of each byte that has been clocked out of the

slave transmitter. The device that acknowledges must

pull-down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH

period of the acknowledge-related clock pulse (set-up and

hold times must be taken into consideration). A master

receiver must signal an end-of-data to the transmitter by

not generating an acknowledge on the last byte that has

been clocked out of the slave. In this event the transmitter

must leave the data line HIGH to enable the master to

generate a STOP condition.

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