HPC-DEV-IBMA datasheet(12/30 Pages) NSC

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Connection Diagrams (Continued)

TLDD10422 – 32

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See NS Package Number VHG80A

Wait States

The HPC46400E provides software selectable Wait States

for access to slower memories and for shared bus applica-

tions The number of Wait States for the CPU are selected

by two bits in the PSW register The number of Wait States

for DMA are selected by a bit in the Message System Con-

figuration register Additionally the RDY input may be used

to extend the RD or WR cycle allowing the HPC to be used

in shared memory applications and allowing the user to in-

terface with slow memories and peripherals

Power Save Modes

Two power saving modes are available on the HPC46400E

HALT and IDLE In the HALT mode all processor activities

are stopped In the IDLE mode the on-board oscillator and

timer T0 are active but all other processor activities are

stopped In either mode on-board RAM registers and IO

are unaffected (except the HDLC and UART which are re-

set)

HALT MODE

The HPC46400E is placed in the HALT mode under soft-

ware control by setting bits in the PSW All processor activi-

ties including the clock and timers are stopped In the

HALT mode power requirements for the HPC46400E are

minimal and the applied voltage (VCC) may be decreased

without altering the state of the machine There are two

ways of exiting the HALT mode via the RESET or the NMI

The RESET input reinitializes the processor Use of the NMI

input will generate a vectored interrupt and resume opera-

tion from that point with no initialization The HALT mode

can be enabled or disabled by means of a control register

HALT enable To prevent accidental use of the HALT mode

the HALT enable register can be modified only once

IDLE MODE

The HPC46400E is placed in the IDLE mode through the

PSW In this mode all processor activity except the on-

board oscillator and Timer T0 is stopped The HPC46400E

resumes normal operation upon timer T0 overflow As with

the HALT mode the processor is also returned to full opera-

tion by the RESET or NMI inputs but without waiting for

oscillator stabilization

SLOW MODE

The HPC46400E is placed in the SLOW mode under soft-

ware control by setting ‘‘SLOW’’ bit in ‘‘FEXT’’ Feature Ex-

tension register In this mode CKI is divided by 4 and each

CK2 cycle will be 8 CKI clock cycles This reduction in fre-

quency of operation of HPC16400E is achieved without al-

tering the state of the machine CKI and CKO signals remain

unaffected reagardless of the status of the SLOW bit At

RESET the ‘‘SLOW’’ bit comes up as 0 ie the clocking of

the HPC46400E is normal Software can cause the division

to be enabled or disabled by writinga1ora0tothe

‘‘SLOW’’ bit Note that when the ‘‘SLOW’’ bit is set to 1

HALT or IDLE power down mode cannot be entered

‘‘SLOW’’ bit has to be cleared to a 0 first

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