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ADE7763ARSRL 数据表(PDF) 48 Page - Analog Devices |
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ADE7763ARSRL 数据表(HTML) 48 Page - Analog Devices |
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48 / 56 page  ADE7763 Rev. A | Page 48 of 56 R/W No. Bits Default Type1 Description Address Name 0x12 WGAIN R/W 12 0x0 S Power Gain Adjust. This is a 12-bit register. Calibrate the active power calculation by writing to this register. The calibration range is ±50% of ll-scale active power. The resolution of the gain adjust is the nominal fu 0.0244%/LSB —see the Calibrating an Energy Meter section. 0x13 WDIV R/W 8 0x0 U GY Active Energy Divider Register. The internal active energy register is divided by the value of this register before being stored in the AENER register. 0x14 CFNUM R/W 12 0x3F U just the output frequency CF Frequency Divider Numerator Register. Ad on the CF pin by writing to this 12-bit read/write register—see the Energy-to-Frequency Conversion section. 0x15 CFDEN R/W 12 0x3F U ency Divider Denominator Register. Adjust the output e nversion section. CF Frequ frequency on the CF pin by writing to this 12-bit read/write register—se the Energy-to-Frequency Co 0x16 IRMS R 24 0x0 U Channel 1 RMS Value (Current Channel). 0x17 VRMS R 24 0x0 U Channel 2 RMS Value (Voltage Channel). 0x18 IRMSOS R/W 12 0x0 S ction Register. Channel 1 RMS Offset Corre 0x19 VRMSOS R/W 12 0x0 S Channel 2 RMS Offset Correction Register. 0x1A VAGAIN R/W 12 0x0 S Apparent Gain Register. Calibrate the apparent power calculation by writing to this register. The calibration range is 50% of the nominal scale real power. The resolut full- ion of the gain adjust is 0.02444%/LSB. 0x1B VADIV R/W er 8 0x0 U Apparent Energy Divider Register. The internal apparent energy regist is divided by the value of this register before being stored in the VAENERGY register. 0x1C LINECYC R/W xFFFF U Line-Cycle Register. This 16-bit et the 16 0 Line Cycle Energy Accumulation Mode register is used during line cycle energy accumulation mode to s number of half line cycles for energy accumulation—see the Line Cycle Energy Accumulation Mode section. 0x1D ZXTOUT R/W 12 0xFFF U e Zero-Crossing Timeout. If no zero crossings are detected on Channel 2 within the time specified in this 12-bit register, the interrupt request lin (IRQ) will be activated—see the Zero-Crossing Detection section. 0x1E SAGCYC R/W 8 0xFF U e SAG output is activated—see the Line Voltage Sag Detection Sag Line Cycle Register. This 8-bit register specifies the number of consecutive line cycles below SAGLVL that is required on Channel 2 before th section. 0x1F SAGLVL R/W 8 0x0 U peak nel 2 the SAG Sag Voltage Level. An 8-bit write to this register determines at what signal level on Chan pin becomes active. The signal must remain low for the number of cycles specified in the SAGCYC register before the SAG pin is activated—see the Line Voltage Sag Detection section. 0x20 IPKLVL R/W 8 0xFF U Channel 1 Peak Level Threshold (Current Channel). This register sets the level of current peak detection. If the Channel 1 input exceeds this level, the PKI flag in the status register is set. 0x21 VPKLVL R/W 8 0xFF U Channel 2 Peak Level Threshold (Voltage Channel). This register sets the level of voltage peak detection. If the Channel 2 input exceeds this level, the PKV flag in the status register is set. 0x22 IPEAK R 24 0x0 U Channel 1 Peak Register. The maximum input value of the current channel, since the last read of the register is stored in this register. 0x23 RSTIPEAK R 24 0x0 U Same as Channel 1 peak register, except that the register contents are reset to 0 after a read. 0x24 VPEAK R 24 0x0 U Channel 2 Peak Register. The maximum input value of the voltage channel, since the last read of the register is stored in this register. 0x25 RSTVPEAK R 24 0x0 U e Same as Channel 2 peak register, except that the register contents ar reset to 0 after a read. 0x26 TEMP R 8 0x0 S Temperature Register. This is an 8-bit register that contains the result of the latest temperature conversion—see the Temperature Measurement section. |
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