数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

HD49335F 数据表(PDF) 27 Page - Renesas Technology Corp

部件名 HD49335F
功能描述  CDS/PGA AND 10-bit A/D TG Converter
PDF  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

HD49335F 数据表(HTML) 27 Page - Renesas Technology Corp

Back Button HD49335F Datasheet HTML 22Page - Renesas Technology Corp HD49335F Datasheet HTML 23Page - Renesas Technology Corp HD49335F Datasheet HTML 24Page - Renesas Technology Corp HD49335F Datasheet HTML 25Page - Renesas Technology Corp HD49335F Datasheet HTML 26Page - Renesas Technology Corp HD49335F Datasheet HTML 27Page - Renesas Technology Corp HD49335F Datasheet HTML 28Page - Renesas Technology Corp HD49335F Datasheet HTML 29Page - Renesas Technology Corp HD49335F Datasheet HTML 30Page - Renesas Technology Corp  
Zoom Inzoom in Zoom Outzoom out
 27 / 30 page
background image
HD49335F/HF
Rev.1.0, Feb.25.2004, page 27 of 29
Example of Recommended External Circuit
• Slave mode
Pin 57(Test1 = Low)
31
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
33
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
24 23 22 21 20 19 18 17
25
26
27
28
29
30
32
50
57 58 59 60 61 62 63 64
56
55
54
53
52
51
49
HD49335
1
µ
1
µ
0.1
47/6
47/6
1000p
100p
XV4
CH1
CH2
CH3
CH4
XSUB
SUB_SW/ADCK_in
SUB_PD
STROB/Vgate
DVSS3
AVSS
ADC_in
BIAS
VRB
VRT
VRM
HD_in
CLK_in
DVSS3
DVDD2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DVSS1,2
ID
XV3
VD_in
AVDD
SCK
0.1
47/6
0.1
0.1
0.1
0.1
3.0V
Reset(Normally Hi)
Reset(Normally Hi)
to CCD
+
+
0.1
33k
to CCD
to CCD
ID pulse
ID pulse
to V.Baff
47
µ
47
µ
47
µ
• Master mode
Pin 57(Test1 = Hi)
31
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
33
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
24 23 22 21 20 19 18 17
25
26
27
28
29
30
32
50
57 58 59 60 61 62 63 64
56
55
54
53
52
51
49
HD49335
1
µ
1
µ
0.1
47/6
47/6
1000p
100p
XV4
CH1
CH2
CH3
CH4
XSUB
SUB_SW/ADCK_in
SUB_PD
STROB/Vgate
DVSS3
AVSS
ADC_in
BIAS
VRB
VRT
VRM
HD_in
CLK_in
DVSS3
DVDD2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DVSS1,2
ID
Unit: R:
C: F
XV3
VD_in
AVDD
SCK
0.1
47/6
0.1
0.1
0.1
0.1
CCD signal input
CCD signal input
3.0V
to CCD
+
+
0.1
33k
∗ 61pin = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
61pin = Hi:
Pin 41 is Vgate output
Pin 39 is Hiz
∗ 61pin = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
61pin = Hi:
Pin 41 is Vgate output
Pin 39 is Hiz
to V.Baff
47
µ
47
µ
47
µ
∗ Pin 56 = Low: TESTIN mode. Please do not use.
Low
Hi
Pin 57
Slave mode
Master mode
Mode
CLK, HD, VD input from SSG.
HD, VD output
Specification
Serial data input
Serial data input
from
Pulse generator
from
Pulse generator
to
Camera
signal
processor
to
Camera
signal
processor
to
Camera
signal
processor



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com