Nexperia

PRMD2

50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

Per transistor, for the PNP transistor with negative polarity

collector-base voltage

open emitter

-

50

V

collector-emitter voltage open base

-

50

V

emitter-base voltage

open collector

-

10

V

input voltage

-10

40

V

output current

-

100

mA

total power dissipation

[1]

-

325

mW

Per device

total power dissipation

[1]

-

480

mW

junction temperature

-

150

°C

ambient temperature

-55

150

°C

storage temperature

-65

150

°C

[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.

-75

175

125

25

75

-25

aaa-024487

200

300

100

400

500

(mW)

0

FR4 PCB, standard footprint

Fig. 1. Per device: Power derating curve

PRMD2

All information provided in this document is subject to legal disclaimers.

Product data sheet

14 September 2018

3 / 14