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INTELLON CONFIDENTIAL
33
ADVANCE INFORMATION
Rev 8.1
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Parameter
Symbol
Parameter Name
Test Condition
Min
Max
Unit
tJTAG_F
TCK Frequency
10
MHz
tJTAG_P
TCK Period
100
ns
tJTAG_H
TCK High Time
@ 2.0V
45
ns
tJTAG_L
TCK Low Time
@ 0.8V
45
ns
tJTAG_R
TCK Rise Time
4
ns
tJTAG_FT
TCK Fall Time
4
ns
tJTAG_SU
TDI, TMS Setup Time
8
ns
tJTAG_H
TDI, TMS Hold Time
10
ns
tJTAG_VD
TDO Valid Delay
3
30
ns
tJTAG_FD
TDO Float Delay
50
ns
tJTAG_OVD
All Outputs (Non-Test) Valid Delay
3
25
ns
tJTAG_OFD
All Outputs (Non-Test) Float Delay
36
ns
tJTAG_ISU
All Inputs (Non-Test) Setup Time
8
ns
tJTAG_IH
All Inputs (Non-Test) Hold Time
7
ns
Table 15: JTAG (IEEE 1149.1) DC Characteristics
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