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Rev 1.0

21/11/19

7. Maximum test duration 2ms, one output loaded at a time.

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

4.5V

4.4

4.4

4.4

5.5V

5.4

5.4

5.4

V

4.5V

3.86

3.76

3.76

5.5V

5

4.86

4.76

4.76

V

4.5V

-

-

3.85

Minimum High-Level

Output Voltage

5.5V

5,6

-

-

3.85

V

Maximum Input

Leakage Current

5.5V

±0.1

±1.0

±1.0

µA

Additional Maximum

5.5V

0.6

1.5

1.5

mA

5.5V

-

75

75

Minimum Dynamic

Output Current

7

5.5V

-

-75

-75

mA

Maximum Quiescent

Supply Leakage

Current

5.5V

4

40

40

µA

 

8. Not production tested in die form, characterized by chip design and tested in package.

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

Maximum Clock

Frequency

5V ±10%

-

145

125

125

MHz

11

13

13

Maximum

Propagation Delay,

CLK to Q or Q

(Figure1)

5V ±10%

10

11.5

11.5

ns

9.5

10.5

10.5

Maximum

Propagation Delay,

PRE or CLR

to Q or Q

(Figure 2)

5V ±10%

10

11.5

11.5

ns

Maximum Input

Capacitance

5V ±10%

GND

4.5

4.5

4.5

pF

TYPICAL

Power Dissipation

Capacitance

9

-

35

pF