CD54HC164 datasheet(6/11 Pages) TI

6 / 11 page

Power Dissipation

Capacitance

(Notes 3, 4)

CPD

HCT TYPES

Propagation Delay,

CP to Qn

tPLH, tPHL

CL = 50pF

4.5

CL = 15pF

MR to Qn

tPLH, tPHL

CL = 50pF

4.5

CL = 15pF

Output Transition Times

tTLH, tTHL

CL = 50pF

4.5

Input Capacitance

CIN

Maximum Clock Frequency

fMAX

CL = 15pF

MHz

Power Dissipation

Capacitance

(Notes 3, 4)

CPD

NOTES:

3. CPD is used to determine the dynamic power consumption, per device.

4. PD =VCC

2 f

i + ∑ (CL VCC

2 +f

O) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply

Voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

VCC (V)

25oC

-40oC TO 85oC

-55oC TO 125oC

UNITS

TYP

MAX

Test Circuits and Waveforms

FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

trCL

tfCL

GND

VCC

GND

VCC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

VCC

50%

90%

10%

50%

90%

tREM

tPLH

tSU(H)

tTLH

tTHL

tH(L)

tPHL

50pF

tSU(L)

tH(H)

trCL

tfCL

GND

1.3V

2.7V

0.3V

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

1.3V

90%

10%

1.3V

90%

tREM

tPLH

tSU(H)

tTLH

tTHL

tH(L)

tPHL

50pF

tSU(L)

1.3V

tH(H)

1.3V

CD54HC164, CD74HC164, CD54HCT164, CD74HCT164

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