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78P7200
E3/DS3/STS-1
Line Interface Unit
Page: 7 of 11
© 2005 Teridian Semiconductor Corporation
Rev 3.0
EXTERNAL COMPONENTS (Dependent on speed, nominal Value)
STS-1
DS3
E3
Loop center frequency resistor RFO
1% tolerance
4.53
5.23
6.81
k
Ω
Transmit termination capacitor CTT
5% (Note 2)
10
10
3
pF
Transmit termination resistor
RTT
1%
301
301
604
Ω
Note 1: Optional capacitor to reduce common mode noise.
Note 2: CTT value depends on the PC board design. Nominal values are selected for 78P7200 Demo Board.
DIGITAL INPUTS AND OUTPUTS
(CMOS-compatible pins:
LOWSIG, RPOS, RNEG, RCLK, TPOS, TNEG, TCLK, LBO, OPT!.) Currents flowing
into the chip are positive. Current maximums are currents with the largest absolute value.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Input low voltage
VIL
-0.3
1.5
V
Input high voltage
VIH
3.5
Vcc
+0.3
V
Input low current
IIL
VIL = 1.5V
-5
5
µA
Input high current
IIH
VIH = 3.5V
-5
5
µA
Output low voltage
VOL
IOL = 0.1 mA
0.4
V
Output high voltage
VOH
IOH = -0.1 mA
4
V
OPT@
OPT@
OPT@
OPT@ CHARACTERISTICS
Input low voltage
VIL
IIL = 0.4 mA
0.5
V
Input high voltage
VIH
2
V
RECEIVER
All of the measurements for the receiver are made with the following conditions unless otherwise stated:
1.
The input signal is transformer coupled as shown in Figure 1.
2.
RFO = 5.23 k
Ω for DS3, 6.81 kΩ for E3 and 4.53 kΩ for STS-1.
Input AC-Coupled
CPD = 0.022 µF
±0.045
±1.2
V
Input signal voltage
VIN
Short cable (3’)
CPD not used
±0.090
±1.2
V
Input Resistance
RIN
Input at device's common mode
voltage
15
20
30
k
Ω
Receive data detection
VDTH
threshold
Relative to peak amplitude for
22.37/17.18/25.92 MHz
sinusoidal input
50
%
Receive data low signal
VLOW
threshold
±20
±50
mV
CPD = 0.022 µF
500
µs
Receive data low signal
TLOW
delay
CPD not used
VIN(max) = ±250 mV
0.5
3
µs
OPT@
OPT@
OPT@
OPT@
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